1. Technical Field
The invention relates generally to semiconductor fabrication, and more particularly, to a metal resistor and resistor material, and a method of forming the metal resistor.
2. Background Art
The resistor is one of the most common electrical components, and is used in almost every electrical device. In semiconductor device fabrication, it is well known to have thin film resistors embedded in the back-end-of-line (BEOL) structures of the chip through either a damascene approach or a subtractive etch method. The BEOL thin film resistors are preferred over other types of resistors because of the lower parasitic capacitance. Conventional resistor materials and fabrication methods, however, present a number of challenges.
In one approach, the sheet resistivity of the various resistors formed over the entire wafer may vary and go beyond specifications due to poor process control. In an advanced manufacturing line, wafers out of speciation are often scrapped for quality control, which is expensive.
One material used for resistors is doped polysilicon. A problem with this conventional resistor material is that it can only provide a limited resistance within a limited dimension, which presents problems as further miniaturization of the device features continues. Resistive thin films such as chromium silicide (CrSi) and tantalum nitride (TaN) are also used as resistors in semiconductor devices.
Integration schemes used to fabricate the resistor components within the interconnect structure fall into two primary categories. In the first integration scheme, a thin film resistor is formed by etching on top of an insulator. A metallic layer is deposited on top of the resistive layer and is used to protect the resistive layer from being damaged during the sequential etching process. After the resistor has been defined, the underneath dielectric is then patterned and etched to define the interconnect pattern. Finally, a metallic layer for the interconnect is deposited, patterned, and etched. This process presents challenges because, although the protective layer is capable of protecting the resistive layer, the provided protection is limited and the resistive layer may still get damaged during the etching process. This approach also requires extra layers, which adds cost and complexity. In the second integration scheme, a thin film resistor is formed by etching on top of an insulator. An interlevel dielectric is then deposited, followed by patterning and etching processes to define an upper level interconnect structure with vias connected to the underneath thin film resistor. A planarization process is usually required after deposition of the interlevel dielectric material in order to compromise any possible topography related issues caused by the underneath resistors. The planarization process adds expense.
Setting the resistance of the resistors also presents challenges. In one approach, resistors can be trimmed using laser or high-energy particle beam to set the resistance thereof. But, these processes are not clean and therefore have never become a common practice. Resistors can also be programmed by using a shunt transistor to deselect at least a portion of the resistor from a chain of the resistor circuit. This approach has at least a couple of problems. First, the resolution of the programming is limited by the least significant bit (LSB) device size, and the shunt device itself has some resistance. The tuning precision using this approach is thus poor.
In view of the foregoing, there is a need in the art for a solution to the problems of the related art.